As process technology has been evolving to submicron geometries, Shallow trench isolation (STI) has been gradually replacing conventional semiconductor device isolating methods such as, for example, local oxidation of silicon (LOCOS). STI provides several major advantages over LOCOS methods. For example, STI methods allow for higher device density by decreasing the required width of the semiconductor device isolating structure. As yet another benefit, STI enhances surface planarity which, in turn, considerably improves critical dimension control during lithography steps.
Referring now to Prior Art FIGS. 1A-1C, side-sectional views illustrating steps used in a prior art STI process are shown. As shown in Prior Art FIG. 1A, a substrate 100 has an oxide 102 and nitride 104 stack formed thereon. The oxide 102 and nitride 104 stack is used as a mask.
As shown in Prior Art FIG. 1B, using conventional masking and photolithography steps, a typical STI process forms an opening 106 extending through the oxide 102 and nitride 104 stack. Opening 106 extends to the top surface of semiconductor substrate 100.
Referring next to FIG. 1C, in a conventional STI process, a plasma etch or other type of dry etch is then used to etch an opening or "trench" 108 into semiconductor substrate 100. In a conventional STI process, a common etch chemistry of chlorine and hydrogen bromide (Cl.sub.2 /HBr) is used to etch trench 108 into semiconductor substrate 100. As shown in the cross-sectional view of trench 108 in Prior Art FIG. 1C, a conventional STI process results in the formation of a trench 108 having micro-trenches 110 and 112 formed into the bottom surface thereof. Thus, a trench formed by a conventional STI process does not have a substantially planar bottom surface. As a result, when a prior art trench 108 is subsequently filled with dielectric material, voids are often created in and around micro-trenches 110 and 112. Such voids reduce semiconductor device isolation effectiveness and device reliability.
As yet another drawback, trench 108, formed by a conventional STI process, has a vertical sidewall profile. That is, sidewalls 113a and 113b are vertically oriented. As a result, adhesion of subsequently deposited dielectric material to sidewalls 113a and 113 is adversely affected. Poor adhesion of the dielectric material to sidewalls 113a and 113b compromises the integrity of the semiconductor isolating device.
Referring still to Prior Art FIG. 1C, conventionally fabricated trench 108 contains yet another substantial disadvantage. Namely, the interface of vertically oriented sidewalls 113a and 113b and the top surface of semiconductor substrate 100 produces sharp corners 114 and 116. As a result, stress in the contact between subsequently deposited dielectric material and semiconductor substrate 100 is generated at sharp corners 114 and 116. Such sharp corners 114 and 116 and resultant stresses contribute to poor leakage protection and poor gate oxide integrity.
Thus, a need exists for semiconductor decive isolating structure which does not have sharp stress-generating corners. A need also exists for a semiconductor device isolating structure which does not have micro-trenches formed therein. A further need exists for a semiconductor device isolating structure which enhances sidewall bonding of a dielectric material thereto.